In order to simplify the hardware design and reduce the resource requirements, this paper\nproposes a novel implementation of a convolutional auto-encoder (CAE) in a field programmable\ngate array (FPGA). Instead of the traditional framework realized in a layer-by-layer way, we designed\na new periodic layer-multiplexing framework for CAE. Only one layer is introduced and periodically\nreused to establish the network, which consumes fewer hardware resources. Moreover, by fixing the\nnumber of channels, this framework can be applicable to an image of arbitrary size. Furthermore,\nto effectively improve the speed of convolution calculation, the parallel convolution method is used\nbased on shift registers. Experimental results show that the proposed CAE framework achieves good\nperformance in image compression. It can be observed that our CAE framework has advantages\nin resources occupation, operation speed, and power consumption, indicating great potential for\napplication in digital signal processing.
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